Center for Quantum Information Physics Seminars

Realizing a below-threshold fault-tolerant quantum processor is the overarching, yet currently compartmentalized, challenge of the quantum research community. Significant progress is being made in each layer of the stack: new high-rate qLDPC error correction codes, better decoder schemes, next-gen FPGA chips for control hardware, and improved architectures and fabrication methods for processor designs across modalities. One final, but crucial, component—what we have been focused on at Harmoniqs—is novel pulse-level control and calibration algorithms to push down physical error rates as far as possible. Roughly, logical error rates depend on two things: the QEC code, constrained by device error channels, topology, and reconfigurability; and the physical gate error rate, determined by how accurately and consistently you can drive your system at the pulse level. In this talk, I will discuss the connections between pulse-level driving and error-channel shaping, how we can optimize processors around the pulses we send into them, and how we envision jointly designing and optimizing QEC operations, control hardware, pulses, and processors.

Epitaxial interfaces often determine the structural and electronic properties of quantum materials, particularly when multiple interactions compete or when chemically dissimilar materials are combined. In this talk, I will discuss two examples in which the buried interface plays a central role in the resulting behavior. First, I will describe remote epitaxy frustration of GdAuGe on graphene/SiC, where the growing film experiences competing periodic potentials from both graphene and the underlying substrate. By tuning the graphene–substrate coupling, we find an intermediate regime in which the interface loses long-range translational order while retaining local atomic order. This structurally frustrated interface exhibits a magnetic response consistent with a strong interfacial contribution, with signatures persisting to room temperature. Second, I will discuss the growth of FeSe on GaAs, where direct integration is limited by interfacial reactions and secondary-phase formation. I will show a low-temperature growth window around 200 °C that suppresses these reactions while maintaining crystalline FeSe and discuss an ultrathin Bi interlayer as a route toward interfacial spin–orbit engineering. Taken together, these studies highlight how buried interfaces can give rise to unexpected structural and magnetic behavior, while also providing a means to control heterogeneous integration in epitaxial quantum materials.